As an exemplary non-volatile semiconductor memory device, a type of non-volatile semiconductor memory device has been conventionally known that accumulates electric charges into a charge accumulation layer of a memory cell transistor by means of, for instance, a quantum tunneling effect in order to execute data writing (e.g., see PTL 1). Actually, as shown in FIG. 6, a non-volatile semiconductor memory device 100 of this type has a structure that higher order bit lines 101a and 101b and word lines 102a to 102h are disposed in an intersecting manner and a plurality of memory cell transistors 103 are disposed in a row and column matrix with respect to the higher order bit lines 101a and 101b and the word lines 102a to 102h.
The higher order bit line 101a is provided with a plurality of first semiconductor switches 104a and 104c, while a single lower order bit line 105a, 105c is connected to each first semiconductor switch 104a, 104c. Further, in this exemplary embodiment, the other higher order bit line 101b is also similarly provided with a plurality of first semiconductor switches 104b and 104d, while a single lower order bit line 105b, 105d is connected to each first semiconductor switch 104b, 104d. In such non-volatile semiconductor memory device 100, each lower order bit line 105a, 105b, 105c, 105d forms a memory block 106a, 106b, 106c, 106d, while each memory block 106a, 106b, 106c, 106d has the plural memory cell transistors 103.
The first semiconductor switches 104a, 104b, 104c and 104d are herein formed by N-MOS (Metal-Oxide-Semiconductor) transistors. Further, the first semiconductor switch 104a of the memory block 106a, for instance, is connected at the source thereof to the higher order bit line 101a while being connected at the drain thereof to the lower order bit line 105a, and is also connected at the gate thereof to a first selected gate line 108a shared with another memory block 106b aligned with the memory block 106a along a row direction. Thus, by this configuration, a predetermined gate voltage can be equally applied from the shared, single first selected gate line 108a to the two first semiconductor switches 104a and 104b that are mounted on the memory blocks 106a and 106b disposed in the upper part of FIG. 6.
On the other hand, similarly also in the two memory blocks 106c and 106d aligned along the row direction in the lower part of FIG. 6, a single first selected gate line 108b is connected to the two first semiconductor switches 104c and 104d, and a predetermined gate voltage is can be configured to be equally applied to the two first semiconductor switches 104c and 104d from the shared, first selected gate line 108b.
In addition to this, a higher order source line 110a is provided with a plurality of second semiconductor switches 111a and 111b, while a single lower order source line 112a, 112b is connected to each second semiconductor switch 111a, 111b. Further, the other higher order source line 110b is also similarly provided with a plurality of second semiconductor switches 111c and 111d, while a single lower order line 112c, 112d is connected to each second semiconductor switch 111c, 111d.
Further, the second semiconductor switches 111a, 111b, 111c and 111d are formed by NMOS transistors that the polarity thereof is the same as that of the first semiconductor switches 104a, 104b, 104c and 104d.
Herein, the second semiconductor switch 111a of the memory block 106a, for instance, is connected at the source thereof to the higher order source line 110a while being connected at the drain thereof to the lower order source line 112a, and is also connected at the gate thereof to a second selected gate line 113a shared with another memory block 106b aligned along the row direction in the upper part. Thus, a predetermined gate voltage can be configured to be equally applied from the shared, single second selected gate line 113a to the two second semiconductor switches 111a and 111b that are mounted on the different memory blocks 106a and 106b disposed in the upper part.
On the other hand, similarly also in the two memory blocks 106c and 106d aligned along the row direction in the lower part, a single second selected gate line 113b is connected to the two second semiconductor switches 111c and 111d, and a predetermined gate voltage can be configured to be equally applied to the two second semiconductor switches 111c and 111d from the shared, second selected gate line 113b.
Further, each memory cell transistor 103 on the memory block 106a, for instance, is connected at one terminal thereof to the lower order bit line 105a while being connected at the other terminal thereof to the lower order source line 112a, and thus, the memory cell transistors 103 are disposed in parallel to each other between the lower order bit line 105a and the lower order source line 112a. The word lines 102a, 102b, 102c and 102d, shared by the memory block 106a and another memory block 106b aligned along the row direction, are connected to control gates of the memory cell transistors 103 of the memory block 106a. Due to this, a predetermined gate voltage can be configured to be equally applied, for instance, from the shared, single word line 102a to one of the memory cell transistors 103 of the memory block 106a in the upper part and one of the memory cell transistors 103 of another memory block 106b aligned with the memory block 106a along the row direction in the upper part.
Incidentally, all the memory cell transistors 103 have the same structure that a channel region is disposed between one terminal and the other terminal, which are formed at a predetermined interval on a semiconductor substrate, and a charge accumulation layer, an interlayer insulation layer and a control gate are sequentially laminated through a tunnel insulation layer on the channel region of the semiconductor substrate. Such memory cell transistors 103 are of an N-channel type, and are capable of executing either data writing by injecting electric charges into the charge accumulation layer or data erasing by extracting the electric charges accumulated into the charge accumulation layer by means of voltage to be applied to the control gate and the region between the one terminal and the other terminal.
The non-volatile semiconductor memory device 100 thus structured can be configured to write data in a predetermined one of the memory cell transistors 103, read data from a predetermined one of the memory cell transistors 103 and erase data written in the memory cell transistors 103 by regulating voltages to be respectively applied to the higher order bit lines 101a and 101b, the higher order source lines 110a and 110b and the word lines 102a to 102h and by controlling on/off states of the first semiconductor switches 104a to 104d and the second semiconductor switches 111a to 111d.
In FIG. 6, the memory cell transistor 103 in the first row of the memory block 106a is set as a selected memory cell transistor 115 in which data is written, whereas all the remaining memory cell transistors 103 are set as non-selected memory cell transistors 116 in which data is not written.
It should be herein noted that for the sake of explanatory convenience, the memory block 106a on which the selected memory cell transistor 115 is disposed will be referred to as a selected block 117, whereas the memory blocks 106b, 106c and 106d on which only the non-selected memory cell transistors 116 are disposed will be referred to as non-selected blocks 118.
Actually in the non-volatile semiconductor memory device 100, for instance, when data is written in only the selected memory cell transistor 115 in the first row of the selected block 117, a high voltage of 12[V] is applied to a word line 120 (hereinafter referred to as a selected word line) that is the one connected to the selected memory cell transistor 115 among the plural word lines 102a to 102h, whereas a low voltage of 4[V] is applied to the word lines 121 (hereinafter referred to as non-selected word lines) that are the other remaining ones among the plural word lines 102a to 102h.
Further, at this time, in the non-volatile semiconductor memory device 100, a low voltage of 0[V] as a writing voltage can be applied to a higher order bit line 122 (herein referred to as a selected bit line) that is the one to which the selected memory cell transistor 115 is connected, whereas a high voltage of 8[V] as a writing prevention voltage can be applied to a higher order bit line 123 (herein referred to as a non-selected bit line) that is the one to which only the non-selected memory cell transistors 116 are connected. Moreover, in the non-volatile semiconductor memory device 100, a gate voltage of 10[V], which is higher than the voltage of the non-selected bit line 123, can be applied to the first semiconductor switches 104a and 104b from the first selected gate line 108a connected to the selected block 117, whereas a gate voltage of 0[V] can be applied to the second semiconductor switches 111a and 111b from the second selected gate line 113a.
Accordingly, in the non-volatile semiconductor memory device 100, the first semiconductor switch 104b on the non-selected bit line 123 is switched on by means of the writing prevention voltage from the non-selected bit line 123 and the gate voltage from the first selected gate line 108a, and a writing prevention voltage of 8[V] can be applied to the non-selected memory cell transistor 116 on the non-selected bit line 123 that intersects with the selected word line 120. At this time, the second semiconductor switches 111a, 111b, 111c and 111d are switched off by applying a voltage of 0[V] thereto from the higher order source lines 110a and 110b and by applying a voltage of 0[V] thereto from the second selected gate lines 113a and 113b, and the lower order source lines 112a, 112b, 112c and 112d can be turned into a floating state.
Thus, in the non-selected memory cell transistor 116 at which the selected word line 120 and the non-selected bit line 123 intersect with each other, a voltage difference is reduced between the control gate and the semiconductor substrate, and as a result, electric charges cannot be injected into the charge accumulation layer without occurrence of a quantum tunneling effect.
Further, at this time, the first semiconductor switch 104a on the selected bit line 122 is switched on by means of the writing voltage from the selected bit line 122 and the gate voltage from the first selected gate line 108a, and a writing voltage of 0[V] can be applied to the selected memory cell transistor 115 on the selected bit line 122 that intersects with the selected word line 120. Accordingly, in the selected memory cell transistor 115 at which the selected word line 120 and the selected bit line 122 intersect with each other, a voltage difference is increased between the control gate and the semiconductor substrate by means of the writing gate voltage applied from the selected word line 120. As a result, a quantum tunneling effect occurs and electric charges can be injected into only the charge accumulation layer of the relevant selected memory cell transistor 115. Consequently, in the non-volatile semiconductor memory device 100, only the selected memory cell transistor 115 can be set to be in a data written state while electric charges are accumulated into the charge accumulation layer thereof.